Senior Digital ASIC Development/Verification Engineer (m/f/d)

Implementation of mixed and full-custom blocks in CMOS in schematics and layout HDL coding in mixed-signal environments Support for top level and block level behavior modelling and chip level physical design Specification Based Simulations, verification on module and chip level with structural and behavior models. Analysis of circuits including process variance Performance reporting and documentation Modeling of the circuits in High Level Languages Verification of digital and analog circuits Provide guidance and advice to team members and managers Collaborate cross-functionally and maintains linkage to Chip Top-Level-, HW-, SW- and Maintenance engineering

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